The present invention relates to a thin-film transistor preferably for use in an active-matrix-addressed liquid crystal display device, contact image sensor and other suitable devices and also relates to a method for fabricating such a transistor.
Recently, an active-matrix-addressed liquid crystal display device has been used as a display device for personal computers, TV sets of a reduced thickness, camcorders and so on. In an active-matrix-addressed liquid crystal display device, a thin-film transistor (TFT) is extensively used as a switching element that selectively turns a pixel ON or OFF. A TFT is provided for each of a huge number of pixels so that each of those pixels has its ON/OFF states controlled by its associated TFT.
When a TFT turns ON responsive a scanning signal that has been applied to the gate of the TFT, a predetermined signal voltage is applied to a pixel electrode, which is connected to the drain of the TFT, by way of a data bus line connected to the source of the TFT. In a liquid crystal display device, the orientation state of its liquid crystal layer changes in accordance with the level of a signal voltage applied to a pixel electrode. And by utilizing this change in orientation, an image is displayed thereon.
In an interval after a predetermined signal voltage has been applied to a pixel electrode and before another signal voltage is newly applied to this pixel electrode (i.e., one frame interval), no scanning signal is applied to the gate of a TFT associated with the pixel electrode. That is to say, the TFT is kept OFF to maintain a predetermined display state by keeping the potential level at the pixel electrode constant during this interval. While the TFT is OFF, the amount of current flowing through the TFT (i.e., leakage current or OFF-state current) is preferably as small as possible. This is because if an excessive amount of OFF-state current flows through the TFT, then the liquid crystal layer cannot maintain its desired orientation state and the resultant display quality deteriorates.
Particularly in a TFT including a polysilicon layer as its semiconductor layer, a greater amount of OFF-state current tends to flow through the TFT as compared to a TFT including an amorphous silicon layer as its semiconductor. This is because field-effect mobility is higher in a polysilicon layer than in an amorphous silicon layer. Accordingly, it is even more difficult to maintain the potential level of a pixel electrode associated with such a TFT.
Also, the higher the definition of a display device, the greater the number of pixels the display device should include. If the number of pixels included in a display device is increased, then each of those pixels should be driven in a shorter period of time. In that case, a greater amount of ON-state current should flow through each TFT.
Furthermore, in a small-sized high-definition liquid crystal display for a liquid crystal projector, for example, the size of each pixel has been further reduced. To increase the brightness of an image presented on such a display, the aperture ratio needs to be increased for each pixel region and each TFT needs to be further downsized. On the other hand, to mass-produce an enormous number of display devices at a high yield, measures should be taken against TFT leakage failures resulting from various types of defects.
In summary, a TFT, particularly one for use to drive its associated pixel in a small-sized high-definition liquid crystal display, preferably has:
1) small leakage current;
2) large ON-state current;
3) small size; and
4) no leakage failures.
A TFT having these advantageous features is disclosed in Japanese Laid-Open Publication No. 7-263705, for example. The TFT has a so-called xe2x80x9cmulti-gate structurexe2x80x9d and a so-called xe2x80x9cLDD (lightly doped drain) structurexe2x80x9d in combination. Hereinafter, the TFT disclosed in this publication will be described with reference to FIG. 11.
In the TFT 90 shown in FIG. 11, a pair of gate electrodes 96a and 96b is formed over a semiconductor thin film 92 with an insulating film 94 interposed therebetween. Channel regions 97a and 97b are defined in parts of the semiconductor thin film 92 that are located under the gate electrodes 96a and 96b, respectively. And the channel regions 97a and 97b are interposed or surrounded by lightly doped regions 98a and 98b and heavily doped regions (i.e., source/drain regions) 99a and 99b. Also, another lightly doped region (intermediate region) 95 is defined between the channel regions 97a and 97b. 
By interposing the lightly-doped region (LDD region) 98b between the drain region (i.e., the heavily doped region) 99b and channel region 97b, the intensity of an electric field is weakened at the end of the drain region 99b, thus reducing the leakage current. Also, this TFT has a multi-gate structure having an equivalent circuit configuration in which two single-gate TFTs are connected in series together. Thus, even if a leakage failure has been caused in one of the two TFTs, the other TFT still serves as a switching element. In this manner, redundancy is ensured for leakage failures.
In addition, in the TFT 90 disclosed in the publication identified above, the length of the intermediate region 95 is smaller than the total length of the lightly doped regions 98a and 98b, thereby increasing the amount of ON-state current. Furthermore, the TFT 90 includes no heavily doped region between the gate electrodes 96a and 96b. Thus, the space between the gate electrodes 96a and 96b may be narrowed, and therefore the TFT 90 may be downsized.
Hereinafter, it will be described with reference to FIGS. 12A through 12G how to fabricate a TFT substrate (including the TFT 90) for a liquid crystal display device.
First, in the process step shown in FIG. 12A, a semiconductor thin film 92 of polysilicon (poly-Si), for example, is deposited on an active region on an insulating substrate 91. Then, a surface portion of the semiconductor thin film 92 is oxidized, for example, thereby forming an insulating film 94 thereon.
Next, in the process step shown in FIG. 12B, dopant ions (e.g., B+ ions) may be implanted at a predetermined dose (of e.g., about 1xc3x971012/cm2 to about 8xc3x971012/cm2) into the entire semiconductor thin film 92 if necessary. In this process step, the characteristic of a channel region for the TFT is determined and the threshold voltage of the TFT is controlled.
Thereafter, in the process step shown in FIG. 12C, gate electrodes 96a and 96b are formed over the semiconductor thin film 92 that has been covered with the insulating film 94. Specifically, the gate electrodes 96a and 96b may be formed by depositing a low-resistivity poly-Si thin film doped with phosphorus on the insulating film 94 and then by patterning the poly-Si thin film into a desired shape. It should be noted that if necessary, a silicon nitride film or any other suitable undercoat film may be formed on the insulating film 94 as shown in FIG. 12C before the gate electrodes 96a and 96b are formed thereon.
Then, in the process step shown in FIG. 12D, dopant ions (e.g., P+ ions) are implanted at a relatively low dose into selected parts of the semiconductor thin film 92 using the gate electrodes 96a and 96b as a mask. In this manner, lightly doped regions are defined in those parts of the semiconductor thin film 92, which are not covered with the gate electrodes 96a and 96b, so as to be self-aligned with the gate electrodes 96a and 96b. 
Subsequently, in the process step shown in FIG. 12E, a resist pattern 93 is defined so as to cover the gate electrodes 96a and 96b entirely and the surface of the insulating film 94 partially. The resist pattern 93 should be formed in such a manner that the right- and left-hand-side edges thereof are spaced apart from the associated side faces of the gate electrodes 96a and 96b by a predetermined distance. Using this resist pattern 93 as a mask, dopant ions (e.g., As+ ions) are implanted at a relatively high dose into the non-masked parts of the lightly doped regions. In this manner, those parts of the lightly doped regions are changed into heavily doped regions, which will be source/drain regions for the TFT.
Thereafter, in the process step shown in FIG. 12F, the TFT formed in this manner is covered with an interlevel dielectric film, the dopants introduced are activated through annealing, and then a contact hole is formed through a part of the interlevel dielectric film that is located over the source region.
Subsequently, in the process step shown in FIG. 12G, a data bus line S made of a conductor is formed so as to make electrical contact with the source region via the contact hole. Next, another insulating film is deposited over the entire surface of the substrate and then another contact hole is formed through a part of the insulating films that is located over the drain region. Then, a transparent electrode (i.e., pixel electrode) P of ITO, for example, is formed inside the contact hole so as to make electrical contact with the drain region. In this manner, a TFT substrate for use in an active-matrix-addressed liquid crystal display device is completed.
As described above, the conventional TFT 90 has the multi-gate structure and can reduce the probability of leakage failures. Also, since the intermediate region is a lightly doped region, the space between the gate electrodes can be narrowed and the TFT can be downsized.
However, the TFT 90 cannot reduce the leakage current and increase the ON-state current at the same time. Specifically, if the dopant concentration of the LDD regions is increased, then the ON-state current of the TFT 90 can be increased but the amount of leakage current flowing therethrough also increases. On the other hand, if the dopant concentration of the LDD regions is decreased, then a decreased amount of leakage current will flow through the TFT 90 but the ON-state current thereof also decreases.
In order to overcome the problems described above, preferred embodiments of the present invention provide (1) a thin-film transistor through which a decreased amount of leakage current and an increased amount of ON-state current flow, (2) a method for fabricating such a transistor and (3) a liquid crystal display device that includes the thin-film transistor of the present invention and that realizes higher display quality.
A thin-film transistor according to the present invention includes a semiconductor layer and multiple gate electrodes that have been formed over the semiconductor layer. The semiconductor layer includes: first and second heavily doped regions, which have a first conductivity type, are spaced apart from each other and serve as source/drain regions; and a plurality of channel regions, which have a second conductivity type, are located between the first and second heavily doped regions so as to face the gate electrodes, and include first and second channel regions. The first channel region is closer to the first heavily doped region than any other one of the channel regions is, while the second channel region is closer to the second heavily doped region than any other one of the channel regions is. The semiconductor layer further includes: an intermediate region, which has the first conductivity type and is located between two mutually adjacent ones of the channel regions; a first lightly doped region, which has the first conductivity type and is located between the first channel region and the first heavily doped region; a second lightly doped region, which has the first conductivity type and is located between the second channel region and the second heavily doped region; a third lightly doped region, which has the first conductivity type, has a carrier concentration different from that of the first lightly doped region and is located between the first lightly doped region and the first channel region; and a fourth lightly doped region, which has the first conductivity type, has a carrier concentration different from that of the second lightly doped region and is located between the second lightly doped region and the second channel region.
In a preferred embodiment of the present invention, the first and second heavily doped regions have substantially the same carrier concentration; the first and second lightly doped regions also have substantially the same carrier concentration; the third and fourth lightly doped regions and the intermediate region also have substantially the same carrier concentration; the carrier concentration of the first heavily doped region is substantially higher than that of the first lightly doped region; and the carrier concentration of the first lightly doped region is substantially higher than that of the third lightly doped region.
In another preferred embodiment, the channel regions, the intermediate region and the third and fourth lightly doped regions of the semiconductor layer have been doped with a dopant of the second conductivity type at substantially the same dose.
In this particular embodiment, the third and fourth lightly doped regions have been doped not only with the dopant of the second conductivity type but also the same dopant of the first conductivity type as a dopant that has been introduced into the first and second lightly doped regions.
More particularly, a difference between the carrier concentration of the third lightly doped region and that of the first lightly doped region may be caused by the dopant of the second conductivity type that has been introduced into the third lightly doped region.
Alternatively, a difference between the carrier concentration of the fourth lightly doped region and that of the second lightly doped region may be caused by the dopant of the second conductivity type that has been introduced into the fourth lightly doped region.
In still another embodiment, the first and second lightly doped regions may have substantially the same length.
In yet another embodiment, the third and fourth lightly doped regions may have substantially the same length.
In yet another embodiment, the intermediate region may have a length smaller than a total length of the first and third lightly doped regions.
In yet another embodiment, the intermediate region may have a length smaller than a total length of the second and fourth lightly doped regions.
An inventive method for fabricating a thin-film transistor includes the steps of: forming a semiconductor thin film on an insulating substrate; doping a first region of the semiconductor thin film, which includes a part that will serve as a channel region, with a first dopant of a first conductivity type; forming at least one gate electrode on the semiconductor thin film so that the part of the semiconductor thin film that will serve as the channel region is covered with the gate electrode; selectively doping a second region of the semiconductor thin film with a second dopant of a second conductivity type using the gate electrode as a mask, the second region including other parts of the first region, except the part that will serve as the channel region, and other parts of the semiconductor thin film that surround the first region; and doping a third region of the semiconductor thin film with a third dopant of the second conductivity type, thereby defining regions that will serve as source/drain regions, the third region being so defined as to be spaced apart, by a predetermined distance, from an outer edge of parts of the semiconductor thin film where the first and second region overlap with each other.
In a preferred embodiment of the present invention, the second and third regions overlap with each other at least partially.
In another preferred embodiment of the present invention, an implant dose of the second dopant is smaller than an implant dose of the third dopant.
A thin-film transistor according to the present invention includes a semiconductor layer and multiple gate electrodes that have been formed over the semiconductor layer. The semiconductor layer includes: first and second heavily doped regions, which are spaced apart from each other and serve as source/drain regions; and a plurality of channel regions, which are located between the first and second heavily doped regions so as to face the gate electrodes and which include first and second channel regions. The first channel region is closer to the first heavily doped region than any other one of the channel regions is, while the second channel region is closer to the second heavily doped region than any other one of the channel regions is. The semiconductor layer further includes: an intermediate region located between two mutually adjacent ones of the channel regions; a first lightly doped region located between the first channel region and the first heavily doped region; and a second lightly doped region located between the second channel region and the second heavily doped region. The first channel region includes a first intrinsic channel region and the second channel region includes a second intrinsic channel region.
In a preferred embodiment of the present invention, the first and second intrinsic channel regions are substantially covered with associated ones of the gate electrodes.
In another preferred embodiment of the present invention, the first channel region includes a doped channel region between the first intrinsic channel region and the intermediate region, while the second channel region includes a doped channel region between the second intrinsic channel region and the intermediate region.
In this particular embodiment, the respective doped channel regions of the first and second channel regions and the intermediate region have preferably been doped with a dopant of a first conductivity type at a predetermined dose.
In still another embodiment, the first and second lightly doped regions may have substantially the same length.
In yet another embodiment, the first and second intrinsic channel regions may have substantially the same length.
In yet another embodiment, the first and second intrinsic channel regions may be each shorter than any of the intermediate region, the first lightly doped region and the second lightly doped region.
An inventive method for fabricating a thin-film transistor includes the steps of: forming a semiconductor thin film on an insulating substrate; doping a first region of the semiconductor thin film with a first dopant of a first conductivity type; forming at least one gate electrode on the semiconductor thin film so that a part of the first region and a part of the semiconductor thin film that surrounds the first region are covered with the gate electrode; selectively doping a second region of the semiconductor thin film with a second dopant of a second conductivity type using the gate electrode as a mask, the second region including at least a part of the first region and other parts of the semiconductor thin film that surround the first region and that are not covered with the gate electrode; and doping a fourth region of the semiconductor thin film with a third dopant of the second conductivity type, the fourth region being so defined as to be spaced apart from a third region of the semiconductor thin film by a predetermined distance, the third region including at least the part of the first region and the part of the semiconductor thin film that is covered with the gate electrode.
In a preferred embodiment of the present invention, the second and fourth regions overlap with each other at least partially.
An active-matrix-addressed liquid crystal display device according to the present invention includes: a substrate, on which the thin-film transistor according to any of the preferred embodiments of the present invention; a data bus line electrically connected to the first heavily doped region of the thin-film transistor; a gate bus line electrically connected to at least one of the gate electrodes of the thin-film transistor; and a pixel electrode electrically connected to the second heavily doped region of the thin-film transistor have been formed; and a liquid crystal layer, which has an optical state changeable with a potential level at the pixel electrode.
It should be noted that the terms xe2x80x9cfirst conductivity typexe2x80x9d and xe2x80x9csecond conductivity typexe2x80x9d are herein used to identify n-type and p-type from each other. In other words, one of n- and p-types will be herein referred to as the xe2x80x9cfirst conductivity typexe2x80x9d and the other will be herein referred to as the xe2x80x9csecond conductivity typexe2x80x9d. That is to say, the first conductivity type is n- or p-type and the second conductivity type is p- or n-type.